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M54HC4020
RAD-HARD 14 STAGE BINARY COUNTER
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HIGH SPEED: fMAX = 70 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 4020 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-070
DILC-16
FPC-16
ORDER CODES
PACKAGE DILC FPC FM M54HC4020D M54HC4020K EM M54HC4020D1 M54HC4020K1
DESCRIPTION The M54HC4020 is an high speed CMOS 14 STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology.
A clear input is used to reset the counter to the all low level state. A high level on CLEAR accomplishes the reset function. A negative transition on the CLOCK input increments the counter by one. For M54HC4020 twelve kind of divided output are provided; 1st and 4th stage to 14th stage. The maximum division available at last stage is 1/16384 x fIN at clock. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION
May 2004
Rev. 1
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M54HC4020
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 10 11 8 16 SYMBOL Q1, Q4 to Q14 CLOCK CLEAR GND VCC NAME AND FUNCTION Parallel Outputs Clock Input (LOW to HIGH, Edge Triggered) Reset Inputs Ground (0V) Positive Supply Voltage
Table 2: Truth Table
CLOCK X CLEAR H L L OUTPUT STATE ALL OUTPUTS = "L" NO CHANGE ADVANCE TO NEXT STATE
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Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 3: Absolute Maximum Ratings
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 300 -65 to +150 265 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
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M54HC4020
Table 4: Recommended Operating Conditions
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
Table 5: Dc Specifications
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 80 A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
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M54HC4020
Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25C Min. Typ. 30 8 7 20 5 4 76 21 18 60 18 15 15 65 70 40 8 7 32 8 7 Max. 75 15 13 50 10 9 145 29 25 140 28 24 4.8 24 28 75 15 13 75 15 13 0 0 0 95 19 16 95 19 16 0 0 0 Value -40 to 85C Min. Max. 95 19 16 65 13 11 180 36 31 175 35 30 4 20 24 110 22 19 110 22 19 0 0 0 -55 to 125C Min. Max. 110 22 19 75 15 13 220 44 38 210 42 36 ns Unit
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (Qn - Qn+1) tPLH tPHL Propagation Delay Time (CLOCK Q1) tPHL Propagation Delay Time (CLEAR - Qn) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLEAR) Minimum Removal Time
ns
ns
ns
fMAX
6.0 30 35
MHz
tW(H) tW(L) tW(H)
ns
ns
tREM
ns
Table 7: Capacitive Characteristics
Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 34 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/ FLOP)
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M54HC4020
Figure 4: Test Circuit
CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
Figure 5: Waveform - Minimum Pulse Width (Clear) And Removal Time (Clear To Clock) (f=1MHz; 50% duty cycle)
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M54HC4020
Figure 6: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Propagation Delay Time, Minimum Pulse Width (Clock) (f=1MHz; 50% duty cycle)
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M54HC4020
DILC-16 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 B b b1 D e e1 e2 e3 F I K L 10.90 1.14 17.65 7.62 7.29 2.1 3.00 0.63 1.82 0.40 0.20 20.06 7.36 0.45 0.254 20.32 7.62 2.54 17.78 7.87 7.49 17.90 8.12 7.70 3.83 12.1 1.5 0.429 0.045 0.695 0.300 0.287 0.88 TYP MAX. 2.71 3.70 1.14 2.39 0.50 0.30 20.58 7.87 MIN. 0.083 0.118 0.025 0.072 0.016 0.008 0.790 0.290 0.018 0.010 0.800 0.300 0.100 0.700 0.310 0.295 0.705 0.320 0.303 0.151 0.476 0.059 0.035 TYP. MAX. 0.107 0.146 0.045 0.094 0.020 0.012 0.810 0.310 inch
0056437F
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FPC-16 MECHANICAL DATA
mm. DIM. MIN. A B C D E F G H L M N 0.38 6.0 18.75 0.33 0.38 4.31 22.0 0.43 6.75 9.76 1.49 0.102 8.76 0.127 8.89 1.27 0.43 0.48 0.015 0.237 0.738 0.013 0.015 0.170 0.867 0.017 TYP 6.91 9.94 MAX. 7.06 10.14 1.95 0.152 9.01 MIN. 0.266 0.384 0.059 0.004 0.345 0.005 0.350 0.050 0.017 0.019 TYP. 0.272 0.392 MAX. 0.278 0.399 0.077 0.006 0.355 inch
F
G
D
H
16
9
A
N
L
1
8
H
E
M
C
B
0016030E
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Table 8: Revision History
Date 10-May-2004 Revision 1 First Release Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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